apex signal, a division of nai, inc. bohemia, ny 11716 usa model pc104- 73ld1 specifications pc104- 73ld1 rev e www.naii.com code: 0vgu1 sheet 1 of 4 pc104-73ld1 four lvdt "programmable" tracking converters with wrap-aroundself test. +5 vdc only features: ? only +5 vdc. ? 16 bit resolution ? accuracy 0.025% fs ? continuous background bit testing with reference and signal loss detection ? 360 hz to 10 khz ? transformer isolated ? programmable reference and signal voltages ? accurate digital velocity outputs ? latch feature ? synthetic reference compensates for 60 phase shift ? no adjustments or trimming required ? 8 bit or 16 bit data bus versions description: this pc104 compliant stackthrough module offers four (4) separate transformer isolated ?programmable? lvdt/rvdt-to-digital tracking converters with extensive diagnostics, digital velocity, and (a+b) outputs. instead of buying cards that are set for specific inputs, the uniqueness of this design makes it possible to order our generic card that is autoranging between 2.0 and 28 volts for 4-wire lvtd input. for 2-wire inputs, the card can be programmed and reprogrammed in the field for any excitation and signal voltage between 2.0 and 28 volts. this card uses a derived reference ratiometric design approach that is insensitive to magnitude, temperature, frequency and phase shift effects. the conversion technique assures that the output will change only when the lvdt position changes and will ignore excitation voltage variations. the ?latch? feature permits the user to read all channels at the same time. reading will unlatch that channel. the converters utilize a type ii servo loop processing technique that enables tracking, at full accuracy, up to the specified rate. intermediate transparent latches, on all data and velocity outputs, guarantee that current valid data is always available for any channel without effecting the tracking performance of the converters. the optional on - board excitation supply can be factory set for a particular voltage and frequency, or can be supplied as field programmable. to simplify logistics, part number, s/n, date code, & rev. are stored in permanent memory locations. major diagnostic are incorporated that offer substantial improvements to system reliability because user is immediately alerted to channel malfunctions. self-test (post) diagnostic can immediately initiate (d3) test. see programming instructions for further details. three different tests (one on-line and two off-line) can be selected: the (d2) test initiates automatic background bit testing. each channel is checked over the signal range to a measuring accuracy 0.1% fs, and each signal and excitation is monitored. results are available in registers the testing is totally transparent to the user, requires no external programming, has no effect on the standard operation of this card and can be enabled or disabled via the bus. the (d3) or post test, if enabled, starts an initiated bit test that disconnects all channels from the outside world and connects them across an internal stimulus that generates and measures multiple voltages to a test accuracy of 0.1%fs. results can be read from status registers. external excitation is not required. the testing is totally transparent to the user, requires no external programming, and can be enabled or disabled via the bus. power-on (post) test can be enabled or disabled via the bus. the (d0) test is used to check the card and the interface. all channels are disconnected from the outside world allowing user to write any number of input voltages to the card and then read the data from the interface. external excitation is not required.
apex signal, a division of nai, inc. bohemia, ny 11716 usa model pc104-73ld1 specifications pc104- 73ld1 rev e www.naii.com code: 0vgu1 sheet 2 of 4 specifications : number of channels: 8 or 16 (see part number) resolution: 16 bit accuracy: 0.025% fs band width: 40 hz at 400 hz; 200hz > 100 hz. bw and tracking rate can easily be customized . input format: lvdt or rvdt input voltage (4-wire): autoranging from 2.0 to 28 vrms. transformer isolated. input voltage (2-wire): 2.0 to 28 vrms programmable with 0.01 v resolution. transformer isolated. excitation voltage (4-wire): not required excitation voltage (2-wire): 2.0 to 28 vrms programmable with 0.01 v resolution. transformer isolated. input impedance: 40 k w min. at 360 hz frequency: 360 hz to 10 khz, broadband phase shift: automatically compe nsates for phase shifts between the transducer excitation and output up to 60 velocity, digital: 16 bit resolution; linearity: 0.1% wrap around self test: three powerful test methods are described in the programming instructions. power: + 5 vdc at 0.35 a 12 vdc at 0.1 a without excitation; 1.1 a for 5 va excitation output temperature, operating: -40c to +80c storage temperature: -55c to +105c size: 4.5 x 13.5 x 0.74 weight: 12 oz. programming instructions: i/o configuration : this card requires 64 consecutive addresses in the i/o address space on a 64 byte boundary. the base address is switch settable in the 000-3e0 hex (0 to 992) address range . address= base + offset base a9 a8 a7 a6 offset a5, a4, a3, a2, a1, a0 decimal equiv. sw4 * 64 sw3 * 128 sw2 * 256 sw1 * 512 * ?1? = off ?0? = on note: base addresses to avoid: 320-32f hard disk 3b0-3bf monochrome display 3f8-3ff asynch comm i/o 378-37f parallel printer port 3f0-3f7 floppy disk offset: page 1 (offset 1f = 0) 00 ch.1 lo read 09 vel.1 hi read 12 status, test read 1a test angle hi read/write 01 ch.1 hi read 0a vel.2 lo read 13 status, test read 1f 0 read/write 02 ch.2 lo read 0b vel.2 hi read 14 test enable read/write 03 ch.2 hi read 10 status, lo read 16 test (d2) verify read/write 08 vel.1 lo read 11 status, hi read 19 test angle lo read/write offset: page 2 (offset 1f = 1) 08 velocity, scale ch.1 lo read/write 12 ref. freq. lo read/write 18 date code lo read 09 velocity, scale ch.1 hi read/write 13 ref. freq. hi read/write 19 date code hi read 0a velocity, scale ch.2 lo read/write 14 p/n lo read 1a rev. level lo read 0b velocity, scale ch.2 hi read/write 15 p/n hi read 1b rev. level hi read 10 ref. eo lo read/write 16 s/n lo read 1c active channels read/write 11 ref. eo hi read/write 17 s/n hi read 1f 1 read/write
apex signal, a division of nai, inc. bohemia, ny 11716 usa model pc104-73ld1 specifications pc104- 73ld1 rev e www.naii.com code: 0vgu1 sheet 3 of 4 offset: page 3 (offset 1f = 2) 00 save write 07 exc. ch.2 hi read/write 0c sig. ch.1 lo read/write 11 sig. ch.3 hi read/write 02 latch write 08 exc. ch.3 lo read/write 0d sig. ch.1 hi read/write 12 sig. ch.4 lo read/write 04 exc. ch.1 lo read/write 09 exc. ch.3 hi read/write 0e sig. ch.2 lo read/write 13 sig. ch.4 hi read/write 05 exc. ch.1 hi read/write 0a exc. ch.4 lo read/write 0f sig. ch.2 hi read/write 14 power-on (post) enable read/write 06 exc. ch.2 lo read/write 0b exc. ch.4 hi read/write 10 sig. ch.3 lo read/write 1f 2 read/write hi byte lo byte d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data sign 5.000 2.500 1.250 .6250 .3125 .1563 .0781 .0391 .0195 .0098 .0049 .0024. .0012 .0006 .0003 data, velocity ( rps) sign d d d d d d d d d d d d d d d latch outputs x x x x x x x x x x x x x x 1 x test enable x x x x x x x x x x x x d3 d2 x d0 active channels x x x x x x x x x x x x ch.4 ch.3 ch.2 ch.1 status, signal x x x x x x x x x x x x ch.4 ch.3 ch.2 ch.1 status, excitation x x x x x x x x x x x x ch.4 ch.3 ch.2 ch.1 status, test x x x x x x x x x x x x ch.4 ch.3 ch.2 ch.1 power on or system reset, unless post (page 3, 1eh is set to (?1?) and saved, disables d3 test, all channels unlatched, excitation supply frequency to 400 hz and output voltage to zero. program required frequency before increasing output voltage. enter all active channels at page 3, 1ah ?1? =active; ?0? =not used. omitting this step will produce false alarms because unused channels will set faults. to save when all channels are programmed, write 5555h at page 1, 1ah. board will clear to hex 00 when save is completed. these settings will repeat until changed. saving is optional. if not saved, reenter at each power on. to restore factory shipped parameters, write aaaah at page 1, 1ah, wait until board writes 00, then do a system reset. data format: two's complement. sign: (d15) 0=in phase; 1= out of phase. offset binary (two?s complement with msb inverted) can be specified. (see part number) the output represents a-b/a+b. max. positive excursion is 7fff, 0=0, and max. negative excursion is 8000. programming signal and reference : the lvdt primary, as usual, is energized by either the excitation output from this card or from an external excitation. the signal voltage to be programmed represents the max. output voltage of the lvdt. the 4-wire lvdt has two output voltages referred to as a and b. when connected to the a and b signal inputs no scaling is required because the inputs are autoranging. for 2-wire lvdt?s scaling is required as follows: set excitation and signal voltages by writing a 16 bit binary word to the appropriate address. ex : 27.11 v signal to ch.2 = 0000101010010111 to page 2, 02h/03h 26.00 v excitation to ch.2 = 0000101000101000 to page 3, 02h/03h. (a+b) output: read binary number and multiply by 0.01 volt. velocity: 16 bit resolution, (15 bit+sign, 2?s compliment); linearity: 0.1%. if velocity scale factor is set to max. ( ffffh), then 1 bit of velocity output = 0.4% fs/sec. ex: if full stroke is 3? (6? total) and you read a velocity output of 630h, then the velocity is 630 x 0.004 x 6 = 15.12 inches/sec status, test: ?1? accuracy ok; ?0? failed. status: ?1? exc. & signal are on; ?0? exc. and/or signal loss. test enable (d2): writing ?1? to d2 at page 2, 1eh, initiates automatic background bit testing each channel is checked over the programmed signal range to a measuring accuracy 0.1%fs, and each signal and excitation is monitored. the results are available in status registers. a ?0? deactivates this test. the testing is totally transparent to the user, requires no external programming, has no effect on the standard operation of this card and can be enabled or disabled via the bus. card will write hex 55 at page 3, 18h when (d2) is enabled. user can periodically clear to hex 00 and then read page 3, 18h again to verify that background bit testing is activated. test enable (d3): power-on (post) if enabled, or writing ?1? to d3 at page 2, 1eh, starts an initiated bit test that disconnects all channels from the outside world and connects them across an internal stimulus that generates multiple test voltages that are measured to a test accuracy and of 0.1%fs. test cycle takes about 10 seconds and results can be read from registers when d3 changes from ?1? to ?0?. external excitation is not required. testing is totally transparent to the user, requires no external programming, and can be enabled or disabled (by setting d3 to ?0?) via the bus.
apex signal, a division of nai, inc. bohemia, ny 11716 usa model pc104-73ld1 specifications pc104- 73ld1 rev e www.naii.com code: 0vgu1 sheet 4 of 4 test enable (d0): checks the card and the interface. writing ?1? to d0 at page 2, 1eh, disconnects all channels from the outside world, allowing user to write any number of input voltages to the card at page 1, 18h/19h, and then read the data from the interface (allow 50 ms after writing). external excitation is not required. connector: samtec tsw-110-25tdra pin sig. lo sig. hi exc. lo exc. hi pin numbers (facing pins from component side of board ) ch. 1 5 6 8 7 19 17 15 13 11 9 7 5 3 1 ch. 2 9 10 12 11 ch. 3 13 14 16 15 ch. 4 17 18 20 19 20 18 16 14 12 10 8 6 4 2 part number designation environmental c = no conformal coating k = removable conformal coating l = permanent conformal coating total number channels options 0 = none 9 = custom (see separate spec) 73ld1- 4 x x x bus 1 = 8-bit isa bus 2 = 16-bit isa bus
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